It is in high demand to improve the strength and the perfection in a device active region of a surface layer of a silicon wafer because of high integration and miniaturization in the device processing. In addition, it is also in high demand to improve the gettering ability to capture impurities such as metal or the like due to bulk micro defects (BMD) formed from an oxygen precipitate or the like within the bulk.
Therefore, oxygen precipitation is promoted by controlling the growth of the grown-in defects as a silicon monocrystalline ingot doped with nitrogen grows with a Czochralski method. The ingot is sliced such that a single crystal silicon wafer is cut away and polished to obtain a mirror surface thereof. Further, a surface layer of the silicon single crystal wafer having mirror polished surfaces is made to be a non-defect layer and a highly concentrated BMD can be built in the bulk by performing a long-term heat treatment (high temperature annealing) at a temperature from 1100 to 1350° C., a heat treatment (RTA processing) that is conducted by a rapid heating and rapid cooling device (rapid thermal annealing device), or a combination thereof, with an argon gas, a hydrogen gas, or the like used as an ambient gas. In this manner, the perfection of the surface layer and the increase of the density of BMD in the bulk are realized (for example, see Patent Reference 1).
However, during the heat treatment as described above, while unnecessary boron, phosphorus, or the like may be deposited onto the surface of the wafer from the ambient atmosphere in the heat treatment furnace, the heat treatment furnace itself, or the like, and boron, phosphorus, or the like contained in the wafer evaporated from a portion of the surface of the wafer may be deposited back onto another portion of the surface of the wafer, such boron, phosphorus, or the like adhered to the surface diffuses from the surface into inside of the wafer such that a carrier density in the surface layer of the wafer may be changed. For this reason, there is provided a method of manufacturing a nitrogen-doped and annealed silicon wafer having the steps of: heat treating a sliced silicon wafer in an ambient atmosphere including one or more of inert gases such as a hydrogen gas; and mirror polishing the silicon wafer after the above-mentioned heat treatment such that a region in which a so-called dopant such as boron, phosphorus, or the like of the surface layer originated from evaporation and deposition has diffused may be removed (for example, see Patent Reference 2).
Further, there is also provided a method of manufacturing a silicon wafer having the steps of: heat treating a silicon wafer prepared by the CZ method in an ambient atmosphere such as a hydrogen gas or the like; heat treating the silicon wafer for oxidization; removing an oxidized film therefrom; and then polishing the silicon wafer for the final mirror surface finish (for example, see Patent Reference 3). Further, it is proposed to perform a heat treatment of a silicon wafer at the temperature from 1100° C. to 1280° C. for one or more hours and a removal process to remove a surface layer with a depth from 0.5 μm to 20 μm in order to improve the hold time of the memory IC (for example, see Patent Reference 4). In addition, it is also proposed to perform a heat treatment of a silicon wafer in an oxidizing atmosphere or an inert atmosphere in a temperature range of 1000° C. to 1300° C. for 0.5 to 5 hours and a mirror polishing of a primary surface of the silicon wafer in order to reduce the number of surface defects and particles on the surface of the silicon wafer (for example, see Patent Reference 5).
In addition, there is disclosed a method of manufacturing a silicon wafer having the steps of: heat treating a mirror polished silicon wafer; and polishing a surface of the wafer having been heat treated such that a haze having occurred, a foreign material having been printed, and a contact mark having been made with a jig during the heat treatment may be removed from the surface of the wafer (for example, see Patent Reference 6). Further, there is disclosed a method of manufacturing a silicon wafer having the steps of: etching a surface of the silicon wafer, heat treating the silicon wafer in a temperature range of 1200 to 1300° C. for 1 to 24 hours; and mirror polishing either or both surfaces of the silicon wafer such that a COP-free region thereof may be expanded, a surface flatness thereof may be improved, scratches thereon may be eliminated, a haze level thereof may be lowered, foreign materials thereon may be prevented from residing on a surface of the silicon wafer, and a substrate resistance value thereof may be kept constant along a depth direction of the silicon wafer by controlling a decrease of boron concentration with respect to a P-type wafer doped with boron (for example, see Patent Reference 7). In addition, a method of manufacturing a silicon wafer having the steps of: heat treating the silicon wafer in an ambient atmosphere including a hydrogen gas; and mirror polishing the heat-treated silicon wafer in order to effectively remove dopant contaminants during the heat treatment is disclosed (for example, see Patent Reference 2).
[Patent Reference 1] Japanese unexamined patent application publication No. 2002-43318
[Patent Reference 2] Japanese unexamined patent application publication No. 2007-242920
[Patent Reference 3] Japanese unexamined patent application publication No. 11-260677
[Patent Reference 4] Japanese granted patent application publication No. 3-19687
[Patent Reference 5] Japanese unexamined patent application publication No. 5-144827
[Patent Reference 6] Japanese unexamined patent application publication No. 2006-4983
[Patent Reference 7] Japanese unexamined patent application publication No. 2003-257981